Structured ASIC have fewer layers to customize which implies much shorter fabrication time. Structured ASICs have fixed layers to incorporate I/Os, RAMs, Power lines, PLLs, and other IP. Structured ASICs are not Gate Arrays. Gate arrays address the manufacturing cycle time issue with custom ASICs. But, Structured ASICs address the design implementation issues with custom ASICS such as NRE charges, time to handoff, cost of design tools and engineering resources, number of design functions to be performed, IP integration, and unpredictable layout turnaround times of custom ASICs.

The Bay Area Chip Design Service Model

In support of the growing trend towards strategic outsourcing and in recognition of high ASIC NRE costs for low and mid volume ASIC designs, Bay Area Chip Design was formed to provide consulting, high-end FPGA conversion, and turn-key ASIC design services. Customers with turnkey approach can provide Bay Area Chip Design with their specification, Verilog/C++ RTL netlist, or gate level Verilog netlist and Bay Area Chip Design delivers timing closure on place and route database to be released to leading foundries.

The Benefits of Outsourcing

To address the issues of mounting design complexity, global competition, resource constraints and time-to-market pressures, more and more semiconductor and system companies are relying upon relationships with external service providers to supply expertise in areas that fall outside of the company’s core competencies and areas of competitive differentiation. These indispensable outsourcing relationships free companies to concentrate their efforts on the areas of greatest value-add, while subsequently allowing the company to benefit from the specialized expertise of external service providers. Such outsourcing arrangements enable companies to introduce new products to the market faster with greater ease.

With today’s $1M NREs, the traditional cell-based implementation approach, once the best compromise between time-to-market and cost, is now delivering swollen die sizes at unattractive prices. Bay Area Chip Design offers IC designers a solution to deep sub-micron IC implementation issues while also delivering application specific area optimization. Bay Area Chip Design gives semiconductor design teams the power to create highly optimized chips at dramatically reduced NRE costs within time-to-market schedule demands. The progressive advances in System-on-a-Chip have made semiconductor designs with high numerical calculation content more ubiquitous. Bay Area Chip Design’s technology is especially suited to deal with DSPs, network processors and microprocessors, the important building blocks within today’s SoCs. Bay Area Chip Design provides solutions for deep sub-micron chip designs with feature sizes below 0.18 micron. Performance objectives are achieved with substantially smaller die, lower power, and lower overall cost of silicon. Please refer to Design Services for more information about the Bay Area Chip Design services offered.